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FEATURES High Accuracy, Supports 50 Hz/60 Hz IEC 687/61036 Less than 0.1% Error over a Dynamic Range of 500 to 1 Compatible with 3-Phase/3-Wire Delta and 3-Phase/ 4-Wire Wye Configurations ADE7752 Supplies Average Real Power on the Frequency Outputs F1 and F2 High Frequency Output CF Is Intended for Calibration and Supplies Instantaneous Real Power Logic Output NEGP Indicates a Potential Miswiring or Negative Power for Each Phase Direct Drive for Electromechanical Counters and 2-Phase Stepper Motors (F1 and F2) Proprietary ADCs and DSP Provide High Accuracy over Large Variations in Environmental Conditions and Time On-Chip Power Supply Monitoring On-Chip Creep Protection (No Load Threshold) On-Chip Reference 2.4 V 8% (20 ppm/ C, Typical) with External Overdrive Capability Single 5 V Supply, Low Power (60 mW, Typical) Low Cost CMOS Process
Polyphase Energy Metering IC with Pulse Output ADE7752*
GENERAL DESCRIPTION
The ADE7752 is a high accuracy polyphase electrical energy measurement IC. The part specifications surpass the accuracy requirements as quoted in the IEC61036 standard. The only analog circuitry used in the ADE7752 is in the ADCs and reference circuit. All other signal processing (e.g., multiplication, filtering, and summation) is carried out in the digital domain. This approach provides superior stability and accuracy over extremes in environmental conditions and over time. The ADE7752 supplies average real power information on the low frequency outputs F1 and F2. These logic outputs may be used to directly drive an electromechanical counter or interface with an MCU. The CF logic output gives instantaneous real power information. This output is intended to be used for calibration purposes. The ADE7752 includes a power supply monitoring circuit on the VDD supply pin. The ADE7752 will remain inactive until the supply voltage on VDD reaches 4 V. If the supply falls below 4 V, the ADE7752 will also be reset and no pulses will be issued on F1, F2, and CF. Internal phase matching circuitry ensures that the voltage and current channels are phase matched. An internal no-load threshold ensures that the ADE7752 does not exhibit any creep when there is no load. The ADE7752 is available in 24-lead SOIC packages.
FUNCTIONAL BLOCK DIAGRAM
ABS
17
VDD 3
IAP 5 IAN 6 VAP 16
ADC HPF ADC PHASE CORRECTION LPF
X
POWER SUPPLY MONITOR
ADE7752
X LPF
2 19
IBP IBN
7
ADC
8
HPF ADC PHASE CORRECTION
DGND CLKIN CLKOUT
VBP 15
20
ICP
9
ICN 10 VCP 14 VN 13 2.4V REF 4k
ADC HPF ADC PHASE CORRECTION LPF
X
DIGITAL-TO-FREQUENCY CONVERTER
*Patent pending.
11
12
4
18
21
22
23
24
1
REV. 0
AGND
REFIN/OUT
NEGP
SCF
S0
S1
F2
F1
CF
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ADE7752-SPECIFICATIONS
Parameter ACCURACY Measurement Error on Current Channel
1, 2
(VDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, TMIN to TMAX = -40 C to +85 C.)
Min Typ Max Unit
Conditions Voltage Channel with Full-Scale Signal ( 500 mV), 25C Over a Dynamic Range 500 to 1
0.1 0.1 0.1
% Reading (Degrees) (Degrees) % Reading
Phase Error between Channels PF = 0.8 Capacitive PF = 0.5 Capacitive AC Power Supply Rejection Output Frequency Variation (CF)
DC Power Supply Rejection Output Frequency Variation (CF) ANALOG INPUTS Maximum Signal Levels Input Impedance (DC) Bandwidth (-3 dB) ADC Offset Error Gain Error REFERENCE INPUT REFIN/OUT Input Voltage Range Input Impedance Input Capacitance ON-CHIP REFERENCE Reference Error Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS ACF, S0, S1, and ABS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS3 F1 and F2 Output High Voltage, VOH Output Low Voltage, VOL CF and NEGP Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY VDD IDD
3
SCF = 0; S0 = S1 = 1 IA = IB = IC = 100 mV rms, VA = VB = VC = 100 mV rms, @ 50 Hz Ripple on VDD of 200 mV rms @ 100 Hz S1 = 1; S0 = SCF = 0 V1 = 100 mV rms, V2 = 100 mV rms VDD = 5 V 250 mV See Analog Inputs Section VAP-VN, VBP-VN, VCP-VN, IAP-IAN, IBP-IBN, ICP-ICN CLKIN = 10 MHz CLKIN/256, CLKIN = 10 MHz See Terminology and Performance Graphs External 2.5 V Reference, IA = IB = IC = 500 mV dc 2.4 V + 8% 2.4 V - 8%
0.01
0.1
% Reading
0.5 370 410 14 9 25
V peak Diff. k kHz mV % Ideal
2.6 2.2 3.3 10
V V k pF mV ppm/C MHz
Nominal 2.4 V 200 25 All Specifications for CLKIN of 10 MHz 10
VDD = 5 V 5% VDD = 5 V 5% Typically 10 nA, VIN = 0 V to VDD
2.4 0.8 3 10
V V A pF
ISOURCE = 10 mA VDD = 5 V ISINK = 10 mA VDD = 5 V VDD = 5 V, ISOURCE = 5 mA VDD = 5 V, ISINK = 5 mA For Specified Performance 5 V 5%
4.5 0.5 4 0.5 4.75 12 5.25 16
V V V V V mA
NOTES 1 See Terminology section for explanation of specifications. 2 See plots in Typical Performance Characteristics graphs. 3 Sample tested during initial release and after any redesign or process change that may affect this parameter. Specifications subject to change without notice.
-2-
REV. 0
ADE7752 TIMING CHARACTERISTICS1, 2 T
Parameter t1 t2 t3 t43, 4 t5 5 t6
3
(VDD = 5 V 5%, AGND = DGND = 0 V, On-Chip Reference, CLKIN = 10 MHz, MIN to TMAX = -40 C to +85 C)
Conditions Unit ms sec sec ms sec sec
275 See Table III 1/2 t2 96 See Table IV CLKIN/4
F1 and F2 Pulsewidth (Logic High) Output Pulse Period. See Transfer Function section. Time between F1 Falling Edge and F2 Falling Edge CF Pulsewidth (Logic High) CF Pulse Period. See Transfer Function section. Minimum Time between F1 and F2 Pulse
NOTES 1 Sample tested during initial release and after any redesign or process change that may affect this parameter. 2 See Figure 1. 3 The pulsewidths of F1, F2, and CF are not fixed for higher output frequencies. See Frequency Outputs section. 4 CF is not synchronous to F1 or F2 frequency outputs. 5 The CF pulse is always 1 s in the high frequency mode. See Frequency Outputs section and Table IV. Specifications subject to change without notice.
t1
F1
t6 t2
F2
t3 t4 t5
CF
Figure 1. Timing Diagram for Frequency Outputs
REV. 0
-3-
ADE7752
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C, unless otherwise noted.)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V Analog Input Voltage to AGND VAP, VBP, VCP, VN, IAP, IAN, IBP, IBN, ICP, and ICN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6 V to +6 V Reference Input Voltage to AGND . . . . -0.3 V to VDD + 0.3 V Digital Input Voltage to DGND . . . . . . -0.3 V to VDD + 0.3 V Digital Output Voltage to DGND . . . . . -0.3 V to VDD + 0.3 V Operating Temperature Range Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
Storage Temperature Range . . . . . . . . . . . . -65C to +150C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150C 24-Lead SOIC, Power Dissipation . . . . . . . . . . . . . . . 88 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 250C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model ADE7752AR ADE7752ARRL EVAL-ADE7752EB
*RW = Small Outline - Wide Body Package in Tubes
Package Description SOIC Package SOIC Package ADE7752 Evaluation Board
Package Option *RW-24 *RW-24 on 13" Reels
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADE7752 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
TERMINOLOGY Measurement Error
ADC Offset Error
The error associated with the energy measurement made by the ADE7752 is defined by the following formula:
Energy Registered by ADE 7752 - True Energy Percentage Error = x 100% True Energy
This refers to the dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see an analog input signal offset. However, as the HPF is always present, the offset is removed from the current channel and the power calculation is not affected by this offset.
Gain Error
Error between Channels
The HPF (high-pass filter) in the current channel has a phase lead response. To offset this phase response and equalize the phase response between channels, a phase correction network is also placed in the current channel. The phase correction network ensures a phase match between the current channels and voltage channels to within 0.1 over a range of 45 Hz to 65 Hz and 0.2 over a range of 40 Hz to 1 kHz. See Figures 12 and 13.
Power Supply Rejection
The gain error of the ADE7752 is defined as the difference between the measured output frequency (minus the offset) and the ideal output frequency. The difference is expressed as a percentage of the ideal frequency. The ideal frequency is obtained from the ADE7752 transfer function. See the Transfer Function section.
PIN CONFIGURATION
CF 1 DGND 2
24 23 22 21
This quantifies the ADE7752 measurement error as a percentage of reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supply (5 V) is taken. A 200 mV rms/100 Hz signal is then introduced onto the supply and a second reading is obtained under the same input signal levels. Any error introduced is expressed as a percentage of reading. See Measurement Error, above. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. The supply is then varied 5% and a second reading is obtained with the same input signal levels. Any error introduced is again expressed as a percentage of reading.
F1 F2 S1 S0 CLKOUT
VDD 3 NEGP 4 IAP 5 IAN 6
CLKIN TOP VIEW IBP 7 (Not to Scale) 18 SCF
19 17 16 15 14 13
ADE7752
20
IBN 8 ICP 9 ICN 10 AGND 11 REFIN/OUT 12
ABS VAP VBP VCP VN
-4-
REV. 0
ADE7752
PIN FUNCTION DESCRIPTION
Pin No. 1 2
Mnemonic CF DGND
Description Calibration Frequency Logic Output. The CF logic output gives instantaneous real power information. This output is intended to be used for calibration purposes. Also see SCF pin description. This provides the ground reference for the digital circuitry in the ADE7752, i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7752 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Power Supply. This pin provides the supply voltage for the digital circuitry in the ADE7752. The supply voltage should be maintained at 5 V 5% for specified operation. This pin should be decoupled to DGND with a 10 F capacitor in parallel with a ceramic 100 nF capacitor. This logic output will go logic high when negative power is detected on any of the three phase inputs, i.e., when the phase angle between the voltage and the current signals is greater than 90. This output is not latched and will be reset when positive power is once again detected. See the Negative Power Information section. Analog Inputs for Current Channel. This channel is intended for use with the current transducer and is referenced in this document as the current channel. These inputs are fully differential voltage inputs with maximum differential input signal levels of 0.5 V. See the Analog Inputs section. Both inputs have internal ESD protection circuitry, and in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This pin provides the ground reference for the analog circuitry in the ADE7752, i.e., ADCs, temperature sensor, and reference. This pin should be tied to the analog ground plane or the quietest ground reference in the system. This quiet ground reference should be used for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, and so on. To keep ground noise around the ADE7752 to a minimum, the quiet ground plane should only connect to the digital ground plane at one point. It is acceptable to place the entire device on the analog ground plane. This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of 2.4 V 8% and a typical temperature coefficient of 20 ppm/C. An external reference source may also be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 F ceramic capacitor. Analog Inputs for the Voltage Channel. This channel is intended for use with the voltage transducer and is referenced as the voltage channel in this document. These inputs are single-ended voltage inputs with maximum signal level of 0.5 V with respect to VN for specified operation. All inputs have internal ESD protection circuitry, and in addition, an overvoltage of 6 V can be sustained on these inputs without risk of permanent damage. This logic input is used to select the way the three active energies from the three phases are summed. This offers the designer the capability to do the arithmetical sum of the three energies (ABS logic high) or the sum of the absolute values (ABS logic low). See the Mode Selection of the Sum of the Three Active Energies section. Select Calibration Frequency. This logic input is used to select the frequency on the calibration output CF. Table IV shows how the calibration frequencies are selected. Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7752. The clock frequency for specified operation is 10 MHz. Ceramic load capacitors of between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to crystal manufacturer's data sheet for load capacitance requirements. A crystal can be connected across this pin and CLKIN as described above to provide a clock source for the ADE7752. The CLKOUT pin can drive one CMOS load when an external clock is supplied at CLKIN or when a crystal is being used. These logic inputs are used to select one of four possible frequencies for the digital-to-frequency conversion. This offers the designer greater flexibility when designing the energy meter. See the Selecting a Frequency for an Energy Meter Application section. Low Frequency Logic Outputs. F1 and F2 supply average real power information. The logic outputs can be used to directly drive electromechanical counters and two-phase stepper motors. See the Transfer Function section.
3
VDD
4
NEGP
5, 6; 7, 8; 9, 10
IAP, IAN; IBP, IBN; ICP, ICN
11
AGND
12
REFIN/OUT
13-16
VN, VCP, VBP, VAP
17
ABS
18 19
SCF CLKIN
20
CLKOUT
21, 22
S0, S1
23, 24
F2, F1
REV. 0
-5-
ADE7752-Typical Performance Characteristics
0.5 0.4 0.3 WYE CONNECTION ON-CHIP REFERENCE PHASE C 1.0 0.8 0.6 WYE CONNECTION ON-CHIP REFERENCE +85 C PF = 1
ERROR - % of Reading
ERROR - % of Reading
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0.1 PHASE B
PHASE A
PHASE A + B + C
0.4 0.2 0 -0.2 +25 C PF = 1
-40 C PF = 1
-0.4 -0.6 -0.8
10 1 CURRENT CHANNEL - % of Full Scale
100
-1.0 0.1
10 1 CURRENT CHANNEL - % of Full Scale
100
TPC 1. Error as a Percent of Reading with Internal Reference (Wye Connection)
TPC 4. Error as a Percent of Reading over Temperature with Internal Reference (Wye Connection)
1.0 0.8 0.6
ERROR - % of Reading
WYE CONNECTION ON-CHIP REFERENCE +85 C PF = +0.5
ERROR - % of Reading
0.5 0.4 0.3
DELTA CONNECTION ON-CHIP REFERENCE
PF = -0.5 PF = +1
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0.1 1 10
+25 C PF = -0.5
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
+25 C PF = +1 -40 C PF = +0.5
PF = +0.5
100
-0.5 0.1
CURRENT CHANNEL - % of Full Scale
10 1 CURRENT CHANNEL - % of Full Scale
100
TPC 2. Error as a Percent of Reading over Power Factor with Internal Reference (Wye Connection)
TPC 5. Error as a Percent of Reading over Power Factor with Internal Reference (Delta Connection)
0.5 0.4 0.3 WYE CONNECTION EXTERNAL REFERENCE +85 C PF = +0.5
ERROR - % of Reading
0.5
WYE CONNECTION 0.4 EXTERNAL REFERENCE 0.3 0.2 0.1 0 +85 C PF = 1
ERROR - % of Reading
0.2 0.1 0 -0.1
+25 C PF = +1
+25 C PF = 1
-0.1 -0.2 -0.3 -0.4 -0.5 0.1 1 10 CURRENT CHANNEL - % of Full Scale 100
-40 C PF = +0.5
-0.2 -0.3 -0.4 -0.5 0.1 +25 C PF = -0.5
-40 C PF = 1
1
10
100
CURRENT CHANNEL - % of Full Scale
TPC 3. Error as a Percent of Reading over Power Factor with External Reference (Wye Connection)
TPC 6. Error as a Percent of Reading over Temperature with External Reference (Wye Connection)
-6-
REV. 0
ADE7752
0.5 0.4 0.3
ERROR - % of Reading
WYE CONNECTION ON-CHIP REFERENCE
18
PF = 1 0.2 0.1 0 -0.1 -0.2 -0.3
15
N: 88 MEAN: 4.48045 SD: 3.23101 MIN: -2.47468 MAX: 12.9385 RANGE: 15.4132
12
PF = 0.5
9
6
3
-0.4 -0.5 45 50 55 FREQUENCY - Hz 60 65
0 -20 -15 -10 -5 0 5 10 15 20
CH_I PhA OFFSET - mV
TPC 7. Error as a Percent of Reading over Frequency with an Internal Reference (Wye Connection)
TPC 9. Channel 1 Offset Distribution
0.5 0.4 0.3 ERROR - % of Reading 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4
WYE CONNECTION EXTERNAL REFERENCE 4.75V
ERROR - % of Reading
0.5 0.4 0.3 WYE CONNECTION ON-CHIP REFERENCE 4.75V
5V
0.2 0.1 0 -0.1
5V
5.25V
5.25V
-0.2 -0.3 -0.4
-0.5 0.1
10 1 CURRENT CHANNEL - % of Full Scale
100
-0.5 0.1
1
10
100
CURRENT CHANNEL - % of Full Scale
TPC 8. Error as a Percent of Reading over Power Supply with External Reference (Wye Connection)
TEST CIRCUIT
10 F I 1k RB 33nF 1k
6
TPC 10. Error as a Percent of Reading over Power Supply with Internal Reference (Wye Connection)
VDD
100nF
3 17
VDD 5 IAP
ABS F1 24 F2 23 825 CF 1 22pF CLKOUT 20 10MHz CLKIN 19 22pF S0 21 S1 22 SCF 18 1k VDD PS2501-1
K7 TO FREQ. COUNTER K8
ADE7752
IAN IBP IBN ICP ICN VAP VBP VCP REFIN/OUT 12
33nF SAME AS IAP, IAN
7 8 9 10 16
SAME AS IAP, IAN 1M 220V 1k 33nF SAME AS VAP SAME AS VAP
15 14
100nF
10 F
NEGP 4 NOT CONNECTED VN AGND DGND
13 11 2
1k 33nF
Test Circuit 1. Test Circuit for Performance Curves
REV. 0
-7-
ADE7752
THEORY OF OPERATION
The six voltage signals from the current and voltage transducers are digitized with ADCs. These ADCs are 16-bit second order sigma-delta with an oversampling rate of 833 kHz. This analog input structure greatly simplifies transducer interface by providing a wide dynamic range for direct connection to the transducer and also simplifying the antialiasing filter design. A high-pass filter in the current channel removes the dc component from the current signal. This eliminates any inaccuracies in the real power calculation due to offsets in the voltage or current signals--see HPF and Offset Effects section. The real power calculation is derived from the instantaneous power signal. The instantaneous power signal is generated by a direct multiplication of the current and voltage signals of each phase. In order to extract the real power component (i.e., the dc component), the instantaneous power signal is low-pass filtered on each phase. Figure 2 illustrates the inst antaneous real power signal and shows how the real power information can be extracted by low-pass filtering the instantaneous power signal. This method is used to extract the real power information on each phase of the polyphase system. The total real power information is then obtained by adding the individual phase real power. This scheme correctly calculates real power for nonsinusoidal current and voltage waveforms at all power factors. All signal processing is carried out in the digital domain for superior stability over temperature and time.
The low frequency output of the ADE7752 is generated by accumulating the total real power information. This low frequency inherently means a long accumulation time between output pulses. The output frequency is therefore proportional to the average real power. This average real power information can, in turn, be accumulated (e.g., by a counter) to generate real energy information. Because of its high output frequency and therefore, shorter integration time, the CF output is proportional to the instantaneous real power. This pulse is useful for system calibration purposes that would take place under steady load conditions.
Power Factor Considerations
The method used to extract the real power information from the individual instantaneous power signal (i.e., by low-pass filtering) is still valid when the voltage and current signals of each phase are not in phase. Figure 3 displays the unity power factor condition and a DPF (displacement power factor) = 0.5, i.e., current signal lagging the voltage by 60, for one phase of the polyphase. If we assume the voltage and current waveforms are sinusoidal, the real power component of the instantaneous power signal (i.e., the dc term) is given by:
V x I x cos (60) 2
V V 2
I I
p(t) = i(t) v(t) WHERE: v(t) = V cos ( t) i(t) = I cos ( t) p(t) = V I {1+ cos (2 t)} 2 TIME INSTANTANEOUS POWER SIGNAL - p(t)
V 2
I
INSTANTANEOUS VA REAL POWER SIGNAL
IA + VB VC IC 2
IB +
HPF IAP IAN ADC MULTIPLIER VAP ADC HPF IBP IBN ADC MULTIPLIER VBP ADC HPF ICP ICN ADC MULTIPLIER VCP VN ADC LPF LPF LPF
ABS INSTANTANEOUS TOTAL POWER SIGNAL
|X|
DIGITAL-TOFREQUENCY F1 F2 |X| DIGITAL-TOFREQUENCY CF
|X|
Figure 2. Signal Processing Block Diagram
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REV. 0
ADE7752
This is the correct real power calculation.
INSTANTANEOUS POWER SIGNAL INSTANTANEOUS REAL POWER SIGNAL
where:
P1 = V1 x I1 cos 1 1 = 1 - 1
(3)
VI 2
PH =
CURRENT VOLTAGE INSTANTANEOUS POWER SIGNAL INSTANTANEOUS REAL POWER SIGNAL
V
n =1
n
x I n cos n
(4)
0V
n = n - n
VI 2
cos(60 ) 0V
As can be seen from Equation 4, a harmonic real power component is generated for every harmonic, provided that harmonic is present in both the voltage and current waveforms. The power factor calculation has previously been shown to be accurate in the case of a pure sinusoid. Therefore the harmonic real power must also correctly account for power factor since it is made up of a series of pure sinusoids. Note that the input bandwidth of the analog inputs is 14 kHz with a master clock frequency of 10 MHz.
VOLTAGE
60
CURRENT
Figure 3. DC Component of Instantaneous Power Signal Conveys Real Power Information PF < 1
Nonsinusoidal Voltage and Current
ANALOG INPUTS Current Channels
The real power calculation method also holds true for nonsinusoidal current and voltage waveforms. All voltage and current waveforms in practical applications will have some harmonic content. Using the Fourier Transform, instantaneous voltage and current waveforms can be expressed in terms of their harmonic content;
v (t ) = VO + 2 x Vn x sin (nt + n )
n =0
The voltage outputs from the current transducers are connected to the ADE7752 current channels, which are fully differential voltage inputs. IAP, IBP, and ICP are the positive input for IAN, IBN, and ICN, respectively. The maximum peak differential signal on the current channel should be less than 500 mV (353 mV rms for a pure sinusoidal signal) for the specified operation.
IAP-IAN
(1)
+500mV IAP DIFFERENTIAL INPUT 500mV MAX PEAK VCM COMMON-MODE 25mV MAX -500mV VCM AGND
where: v(t) VO Vn n is the instantaneous voltage is the average value is the rms value of voltage harmonic n is the phase angle of the voltage harmonic
IA
IAN
i(t ) = IO + 2 x Vn I x sin (nt + n)
n =0
(2)
Figure 4. Maximum Signal Levels, Current Channel
where: i(t) IO In
n
is the instantaneous current is the dc component is the rms value of current harmonic n is the phase angle of the current harmonic
The diagram in Figure 4 illustrates the maximum signal levels on IAP and IAN. The maximum differential voltage between IAP and IAN is 500 mV. The differential voltage signal on the inputs must be referenced to a common mode, e.g., AGND. The maximum common-mode signal shown in Figure 4 is 25 mV.
Voltage Channels
Using Equations 1 and 2, the real power P can be expressed in terms of its fundamental real power (P1) and harmonic real power (PH).
P = P1 + PH
The output of the line voltage transducer is connected to the ADE7752 at this analog input. Voltage channels are a pseudodifferential voltage input. VAP, VBP, and VCP are the positive input with respect to VN. The maximum peak differential signal on the voltage channel is 500 mV (353 mV rms for a pure sinusoidal signal) for specified operation.
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ADE7752
Figure 5 illustrates the maximum signal levels that can be connected to the ADE7752 voltage channels.
VAP-VN +500mV VAP DIFFERENTIAL INPUT 500mV MAX PEAK VCM COMMON-MODE 25mV MAX -500mV VCM AGND VA VN
Meter Connections
In 3-phase service, two main power distribution services exist: 3phase 4-wire or 3-phase 3-wire. The additional wire in the 3-phase 4-wire arrangement is the Neutral wire. The voltage lines have a phase difference of 120 ( 2/3 radians) between each other. See Equation 5.
V A(t ) = 2 x V A x cos ( l t ) 2 VB (t ) = 2 x VB x cos l t + 3 4 VC (t ) = 2 x VC x cos l t + 3
Where VA, VB, and VC represent the voltage rms value of the different phases The current inputs are represented by Equation 6,
I A(t ) = 2 I A x cos ( l t + A ) 2 I B (t ) = 2 I B x cos l t + + B 3 4 + C IC (t ) = 2 IC x cos l t + 3
(5)
Figure 5. Maximum Signal Levels, Voltage Channel
Voltage channels must be driven from a common-mode voltage, i.e., the differential voltage signal on the input must be referenced to a common mode (usually AGND). The analog inputs of the ADE7752 can be driven with common-mode voltages of up to 25 mV with respect to AGND. However, best results are achieved using a common mode equal to AGND.
TYPICAL CONNECTION DIAGRAMS Current Channel Connection
Figure 6 shows a typical connection diagram for the one current channel (IA). A CT (current transformer) is the current transducer selected for this example. Notice the common-mode voltage for the current channel is AGND and is derived by center tapping the burden resistor to AGND. This provides the complementary analog input signals for IAP and IAN. The CT turns ratio and burden resistor Rb are selected to give a peak differential voltage of 500 mV at maximum load.
CT Rb Rf Cf 500mV IAP IAN
(6)
Where IA, IB, and IC represent the rms value of the current of each phase and A, B, and C the phase difference of the current and voltage channel of each phase. The instantaneous powers can then be calculated as follows: P A (t ) = V A (t ) x I A (t ) PB (t ) = VB (t ) x I B (t ) PC (t ) = VC (t ) x IC (t ) Then:
PA(t ) = V A x I A x cos( A ) - V A x I A x cos (2 l t + A ) 4 PB (t ) = VB x I B x cos( B ) - VB x I B x cos 2 l t + + B 3 8 PC (t ) = VC x IC x cos(C ) - VC x IC x cos 2 l t + + C 3
IP PHASE NEUTRAL AGND
Rf
Cf
Figure 6. Typical Connection for Current Channels
Voltage Channels Connection
Figure 7 shows two typical connections for the voltage channel. The first option uses a PT (potential transformer) to provide complete isolation from the main voltage. In the second option, the ADE7752 is biased around the neutral wire, and a resistor divider is used to provide a voltage signal proportional to the line voltage. Adjusting the ratio of Ra, Rb, and VR is also a convenient way of carrying out a gain calibration on the meter.
PT 500mV Rf AGND PHASE NEUTRAL Cf Cf Rf Cf VAP VN
(7)
As can be seen from Equation 7, in the ADE7752, the real power calculation per phase is made when current and voltage inputs of the one phase are connected to the same channel (A, B, or C). Then the summation of each individual real power calculation gives the total real power information. P(t) = PA(t) + PB(t) + PC(t).
Ra* Rb* VR*
500mV Rf Cf
VAP VN
PHASE NEUTRAL
*Ra >> Rf + VR; *Rb + VR = Rf
Figure 7. Typical Connections for Voltage Channels
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ADE7752
Figure 8 demonstrates the connections of the analog inputs of the ADE7752 with the power lines in a 3-phase 3-wire Delta service.
Ra* Rb* VR* Rb* CT PHASE A PHASE C SOURCE Rf CT PHASE B ANTIALIASING FILTERS IBP IBN VBP
INTERNAL RESET INACTIVE ACTIVE INACTIVE 5V 4V
at power-up and power-down. The power supply monitor has builtin hysteresis and filtering. This gives a high degree of immunity to false triggering due to noisy supplies. As can be seen from Figure 10, the trigger level is nominally set at 4 V. The tolerance on this trigger level is about 5%. The power supply and decoupling for the part should be such that the ripple at VDD does not exceed 5 V 5% as specified for normal operation.
VDD
Cf
VAP IAP IAN ANTIALIASING FILTERS
VN Cf
LOAD
0V TIME
Ra* Rb* VR*
Cf
Rb*
*Ra >> Rf + VR; *Rb + VR = Rf
Figure 10. On-Chip Power Supply Monitor
HPF and Offset Effects
Figure 8. 3-Phase 3-Wire Meter Connection with ADE7752
Note that only two current inputs and two voltage inputs of the ADE7752 are used in this case. The real power calculated by the ADE7752 does not depend on the selected channels. Figure 9 demonstrates the connections of the analog inputs of the ADE7752 with the power lines in a 3-phase 4-wire Wye service.
Ra* Rb* VR* Rb* CT ANTIALIASING FILTERS CT PHASE A SOURCE PHASE B Ra* Rb* PHASE C VR* CT Cf Rb* ANTIALIASING FILTERS IBP IBN VBP VAP IAP IAN Cf
Figure 11 shows the effect of offsets on the real power calculation. As can be seen, an offset on the current channel and voltage channel contribute a dc component after multiplication. Since this dc component is extracted by the LPF and is used to generate the real power information for each phase, the offsets will have contributed a constant error to the total real power calculation. This problem is easily avoided by the HPF in the current channels. By removing the offset from at least one channel, no error component can be generated at dc by the multiplication. Error terms at cos(t) are removed by the LPF and the digital-to-frequency conversion. See the Digital-to-Frequency Conversion section.
{V cos(t ) + VOS } x {I cos(t ) + IOS } =
V xI + VOS x IOS + VOS x I cos(t ) + IOS x V cos(t ) 2 V xI + x cos(2t ) 2
Ra* Rb* VR* Rf
Cf Rb*
ANTIALIASING FILTERS ICP ICN VCP LOAD
VOS
IOS V 2 I
DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION
VN
IOS
V I 2
CF
*Ra >> Rf + VR; *Rb + VR = Rf
0
VOS
Figure 9. 3-Phase 4-Wire Meter Connection with ADE7752
POWER SUPPLY MONITOR
FREQUENCY - RAD/S
Figure 11. Effect of Channel Offset on the Real Power Calculation
The ADE7752 contains an on-chip power supply monitor. The power supply (VDD) is continuously monitored by the ADE7752. If the supply is less than 4 V 5%, the outputs of the ADE7752 will be inactive. This is useful to ensure correct device start-up REV. 0 -11-
ADE7752
The HPF in the current channels have an associated phase response that is compensated for on-chip. Figures 12 and 13 show the phase error between channels with the compensation network. The ADE7752 is phase compensated up to 1 kHz as shown. This ensures correct active harmonic power calculation even at low power factors.
0.07 0.06 0.05
Where 8 Hz is the -3 dB cutoff frequency of the low-pass filter. For a line frequency of 50 Hz, this would give an attenuation of the 2 (100 Hz) component of approximately -22 dB. The dominating harmonic will be twice the line frequency, i.e., cos (2t), due to the instantaneous power signal. Figure 14 shows the instantaneous real power signal at the output of the CF, which still contains a significant amount of instantaneous power information, i.e., cos (2t). This signal is then passed to the digital-to-frequency converter where it is integrated (accumulated) over time to produce an output frequency. This accumulation of the signal will suppress or average out any non-dc component in the instantaneous real power signal. The average value of a sinusoidal signal is zero. Thus, the frequency generated by the ADE7752 is proportional to the average real power. Figure 14 shows the digital-to-frequency conversion for steady load conditions, i.e., constant voltage and current. As can be seen in the diagram, the frequency output CF varies over time, even under steady load conditions. This frequency variation is primarily due to the cos(2t) components in the instantaneous real power signal. The output frequency on CF can be up to 160 times higher than the frequency on F1 and F2. The higher output frequency is generated by accumulating the instantaneous real power signal over a much shorter time, while converting it to a frequency. This shorter accumulation period means less averaging of the cos(2t) component. As a consequence, some of this instantaneous power signal passes through the digital-to-frequency conversion. This will not be a problem in the application. Where CF is used for calibration purposes, the frequency should be averaged by the frequency counter. This will remove any ripple. If CF is being used to measure energy, e.g., in a microprocessor based application, the CF output should also be averaged to calculate power. Because the outputs F1 and F2 operate at a much lower frequency, much more averaging of the instantaneous real power signal is carried out. The result is a greatly attenuated sinusoidal content and a virtually ripple-free frequency output.
Mode Selection of the Sum of the Three Active Energies
PHASE - Degrees
0.04 0.03 0.02 0.01 0 -0.01
0
100
200
300
400 500 600 700 FREQUENCY - Hz
800
900 1000
Figure 12. Phase Error between Channels (0 Hz to 1 kHz)
0.010 0.008 0.006
PHASE - Degrees
0.004 0.002 0 -0.002 -0.004
40
45
50
55 60 FREQUENCY - Hz
65
70
Figure 13. Phase Error between Channels (40 Hz to 70 Hz)
DIGITAL-TO-FREQUENCY CONVERSION
As previously described, after multiplication the digital output of the low-pass filter contains the real power information of each phase. However since this LPF is not an ideal "brick wall" filter implementation, the output signal also contains attenuated components at the line frequency and its harmonics, i.e., cos(ht) where h = 1, 2, 3, . . . The magnitude response of the filter is given by: H( f ) = 1 f 1+ 8
2
The ADE7752 can be configured to execute the arithmetic sum of the three active energies, Wh = WhA + WhB + WhC, or the sum of the absolute value of these energies, Wh = |WhA| + | WhB| + |WhC|. The selection between the two modes can be made by setting the ABS pin. Logic high and logic low applied on the ABS pin correspond to the arithmetic sum and the sum of absolute values, respectively.
(8)
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ADE7752
VA LPF MULTIPLIER IA DIGITAL-TOFREQUENCY VB LPF MULTIPLIER IB |X| DIGITAL-TOFREQUENCY CF F1 F2 |X| F1 ABS
FREQUENCY
TIME CF
VC LPF MULTIPLIER IC LPF TO EXTRACT REAL POWER (DC TERM) |X| VI 2
FREQUENCY
TIME
cos(2 t) ATTENUATED BY LPF
0
2 FREQUENCY - RAD/S
INSTANTANEOUS REAL POWER SIGNAL (FREQUENCY DOMAIN)
Figure 14. Real Power-to-Frequency Conversion
When the sum of the absolute values is selected, the active energy from each phase is always counted positive in the total active energy. It is particularly useful in 3-phase 4-wire installation where the sign of the active power should always be the same. If the meter is misconnected to the power lines, i.e., CT connected in the wrong direction, the total active energy recorded without this solution can be reduced by two-thirds. The sum of the absolute values assures that the active energy recorded represents the actual active energy delivered. In this mode, the Reverse Power pin still detects when negative power is present on any of the three phase inputs.
Power Measurement Considerations
(See Table III.) This means that the frequency at these outputs is generated from real power information accumulated over a relatively long period of time. The result is an output frequency that is proportional to the average real power. The averaging of the real power signal is implicit to the digital-to-frequency conversion. The output frequency or pulse rate is related to the input voltage signals by the following equation:
Freq = 6.626 x (VAN x I A + VBN x IB + VCN x IC ) x F 1 - 5 VREF
2
Calculating and displaying power information will always have some associated ripple that will depend on the integration period used in the MCU to determine average power and also the load. For example, at light loads, the output frequency may be 10 Hz. With an integration period of 2 seconds, only about 20 pulses will be counted. The possibility of missing 1 pulse always exists as the ADE7752 output frequency is running asynchronously to the MCU timer. This would result in a 1-in-20 or 5% error in the power measurement.
TRANSFER FUNCTION Frequency Outputs F1 and F2
where: Freq = Output frequency on F1 and F2 (Hz) VAN, VBN, and VCN = Differential rms voltage signal on voltage channels (volts) IA, IB, and IC = Differential rms voltage signal on current channels (volts) VREF = The reference voltage (2.4 V 8%) (volts) F1-5 = One of five possible frequencies selected by using the logic inputs SCF, S0, and S1. See Table II.
Table II. F1-5 Frequency Selection
The ADE7752 calculates the product of six voltage signals (on current channel and voltage channel) and then low-pass filters this product to extract real power information. This real power information is then converted to a frequency. The frequency information is output on F1 and F2 in the form of active high pulses. The pulse rate at these outputs is relatively low, e.g., 32.91 Hz maximum for ac signals with SCF = 1; S0 = S1 = 1.
SCF 1 0
S1 1 1 1 0 0
S0 1 1 0 1 0
F1-5 (Hz) 0.596 76.3 19.07 4.77 1.19
XTAL/CLKIN* 10 MHz/224 10 MHz/217 10 MHz/219 10 MHz/221 10 MHz/223
*F1-5 is a binary fraction of the master clock and therefore will vary if the specified CLKIN frequency is altered.
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Example 1
Thus if full-scale differential dc voltages of +500 mV are applied to VA, VB, VC, IA, IB, and IC respectively (500 mV is the maximum differential voltage that can be connected to current and voltage channels), the expected output frequency is calculated as follows: F1-5 = 0.596 Hz , SCF = S 0 = S1 = 1 V AN = VBN = VCN = IA = IB = IC = 500 mV dc = 0.5 V (rms of dc = dc ) VREF = 2.4 V (nominal reference value ) Note that if the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%.
Freq = 3 x
Example 2
As the voltage and current inputs respect Equations 5 and 6, the total real power (P) is: P = (VA - VC ) ( IAP - IAN ) + (VB - VC ) x ( IBP - IBN )
4 P = 2 x V A x cos( l t ) - 2 x VC x cos l t + 3 x 2 x I A x cos( l t ) 4 2 + 2 x VB x cos l t + - v 2 x VC x cos l t + 3 3 2 x 2 x I B x cos l t + 3 For simplification, we assume that A = B = C = 0 and VA = VB = VC = V. The preceding equation becomes:
6.626 x 0.5 x 0.5 x 0.596 = 0.514 Hz 2.42
P = 2 x V x I A x sin
2 2 x sin l t + x cos l t 3 3
()
In this example, with ac voltages of 500 mV peak applied to the voltage channels and current channels, the expected output frequency is calculated as follows:
2 (9) + 2 x V x I B x sin x sin (l t + ) x cos l t + 3 3 P then becomes:
2 2 P = VAN x I A x sin + sin 2l t + 3 3 + VBN x I B x sin + sin 2l t + 3 3
F1-5 = 0.596 Hz , SCF = S 0 = S1 = 1 V AN = VBN = VCN = IA = IB = IC = 500 mV peak AC = VREF 0.5 V rms 2 = 2.4 V (nominal reference value )
(10)
where: VAN = V sin(2/3) and VBN = V sin (/3) As the LPF on each channel eliminates the 2l component of the equation, the real power measured by the ADE7752 is:
Note that if the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%.
Freq = 3 x 6.626 x 0.5 x 0.5 x 0.596 2 x 2 x 2.42 = 0.26 Hz
P = V AN x I A x
As can be seen from these two example calculations, the maximum output frequency for ac inputs is always half of that for dc input signals. The maximum frequency also depends on the number of phases connected to the ADE7752. In a 3-phase 3-wire Delta service, the maximum output frequency is different from the maximum output frequency in a 3-phase 4-wire Wye service. The reason is that there are only two phases connected to the analog inputs, but also that in a Delta service, the current channel input and voltage channel input of the same phase are not in phase in normal operation.
Example 3
If full-scale ac voltage of 500 mV peak is applied to the voltage channels and current channels, the expected output frequency is calculated as follows:
F1-5 = 0.596 Hz , SCF = S 0 = S1 = 1 V AN = VBN = IA = IB = IC = 500 mV peak ac = VCN = IC = 0 VREF = 2.4 V (nominal reference value ) Note that if the on-chip reference is used, actual output frequencies may vary from device to device due to reference tolerance of 8%. 0.5 2 V rms
3 3 + VBN x I B x 2 2
In this example, the ADE7752 is connected to a 3-phase 3-wire Delta service as shown in Figure 8. The total real energy calculation processed in the ADE7752 can be expressed as: Total Real Power = (VA - VC ) x I A + (VB - VC ) x I B Where VA, VB, and VC represent the voltage on phase A, B, and C, respectively. IA and IB represent the current on phase A and B, respectively.
Freq = 2 x
6.626 x 0.5 x 0.5 x 0.596 2 x 2 x 2.4
2
x
3 = 0.148 Hz 2
Table III shows a complete listing of all maximum output frequencies when using all three channel inputs.
Table III. Maximum Output Frequency on F1 and F2
SCF 1 0 - - - -14-
S1 1 1 1 0 0
S0 1 1 0 1 0
Max Frequency for DC Inputs (Hz) 0.51 65.83 16.46 4.11 1.03
Max Frequency for AC Inputs (Hz) 0.26 32.91 8.23 2.06 0.51 REV. 0
ADE7752
Frequency Output CF
The pulse output CF (calibration frequency) is intended for use during calibration. The output pulse rate on CF can be up to 160 times the pulse rate on F1 and F2. The lower the F1-5 frequency selected, the higher the CF scaling. Table IV shows how the two frequencies are related, depending on the states of the logic inputs S0, S1, and SCF. Because of its relatively high pulse rate, the frequency at this logic output is proportional to the instantaneous real power. As is the case with F1 and F2, the frequency is derived from the output of the low-pass filter after multiplication. However, because the output frequency is high, this real power information is accumulated over a much shorter time. Thus less averaging is carried out in the digital-tofrequency conversion. With much less averaging of the real power signal, the CF output is much more responsive to power fluctuations. See the Signal Processing Block Diagram in Figure 2.
Table IV. Maximum Output Frequency on CF
The F1-5 frequencies allow complete coverage of this range of output frequencies on F1 and F2. When designing an energy meter, the nominal design voltage on the voltage channels should be set to half scale to allow for calibration of the meter constant. The current channel should also be no more than half scale when the meter sees maximum load. This will allow overcurrent signals and signals with high crest factors to be accommodated. Table VI shows the output frequency on F1 and F2 when all six analog inputs are half-scale.
Table VI. F1 and F2 Frequency with Half-Scale AC Inputs
SCF 1 0 - - -
S1 1 1 1 0 0
S0 1 1 0 1 0
F1-5 0.596 76.3 19.07 4.77 1.19
Frequency on F1 and F2 (Half-Scale AC Inputs) 0.06 8.23 2.06 0.51 0.13
SCF 1 0 1 0 1 0 1 0
S1 1 1 1 1 0 0 0 0
S0 1 1 0 0 1 1 0 0
F1-5 (Hz) 0.596 76.29 19.07 19.07 4.77 4.77 1.19 1.19
CF Max for AC Signals (Hz) 16 F1, F2 = 4.11 8 F1, F2 = 263.31 8 F1, F2 = 65.83 16 F1, F2 = 131.66 16 F1, F2 = 32.91 160 F1, F2 = 329.14 8 F1, F2 = 4.11 160 F1, F2 = 82.29 When selecting a suitable F1-5 frequency for a meter design, the frequency output at IMAX (maximum load) with a meter constant of 100 imp/kWhr should be compared with Column 5 of Table VI. The frequency that is closest in Table VI will determine the best choice of frequency (F1-5). For example, if a 3-phase 4-wire Wye meter with a maximum current of 25 A is being designed, the output frequency on F1 and F2 with a meter constant of 100 imp/kWhr is 0.458 Hz at 25 A and 220 V (from Table V). Looking at Table VI, the closest frequency to 0.458 Hz in Column 5 is 0.51 Hz. Therefore F1-5 = 4.77 Hz is selected for this design.
Frequency Outputs
SELECTING A FREQUENCY FOR AN ENERGY METER APPLICATION
As shown in Table II, the user can select one of five frequencies. This frequency selection determines the maximum frequency on F1 and F2. These outputs are intended to be used to drive the energy register (electromechanical or other). Since only five different output frequencies can be selected, the available frequency selection has been optimized for a 3-phase 4-wire service with a meter constant of 100 imp/kWhr and a maximum current of between 10 A and 100 A. Table V shows the output frequency for several maximum currents (IMAX) with a line voltage of 220 V (phase neutral). In all cases, the meter constant is 100 imp/kWhr.
Table V. F1 and F2 Frequency at 100 imp/kWhr
Figure 1 shows a timing diagram for the various frequency outputs. The outputs F1 and F2 are the low frequency outputs that can be used to directly drive a stepper motor or electromechanical impulse counter. The F1 and F2 outputs provide two alternating high going pulses. The pulsewidth (t1) is set at 275 ms, and the time between the rising edges of F1 and F2 (t3) is approximately half the period of F1 (t2). If, however, the period of F1 and F2 falls below 550 ms (1.81 Hz), the pulsewidth of F1 and F2 is set to half of their period. The maximum output frequencies for F1 and F2 are shown in Table III. The high frequency CF output is intended to be used for communications and calibration purposes. CF produces a 96 ms-wide active high pulse (t4) at a frequency proportional to active power. The CF output frequencies are given in Table IV. As in the case of F1 and F2, if the period of CF (t5) falls below 192 ms, the CF pulsewidth is set to half the period. For example, if the CF frequency is 20 Hz, the CF pulsewidth is 25 ms. One exception to this is when the mode is S0 = 1, SCF = S1 = 0. In this case, the CF pulsewidth is 66% of the period.
IMAX (A) 10 25 40 60 80 100
F1 and F2 (Hz) 0.183 0.458 0.733 1.1 1.47 1.83
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NO LOAD THRESHOLD NEGATIVE POWER INFORMATION
The ADE7752 also includes "no load threshold" and "start-up current" features that eliminate any creep effects in the meter. The ADE7752 is designed to issue a minimum output frequency. Any load generating a frequency lower than this minimum frequency will not cause a pulse to be issued on F1, F2, or CF. The minimum output frequency is given as 0.005% of the fullscale output frequency for each of the F1-5 frequency selections or approximately 0.00204% of the F1-5 frequency. See Table VII. For example, an energy meter with a meter constant of 100 imp/kWhr using F1-5 (4.77 Hz), the minimum output frequency at F1 or F2 would be 10.3 10-5 Hz. This would be 1.65 10-3 Hz at CF (16 F1 Hz). In this example, the no load threshold would be equivalent to 3.7 of load or a startup current of 17 mA at 220 V.
Table VII. CF, F1, and F2 Minimum Frequency at No Load Threshold
The ADE7752 detects when the current and voltage channels of any of the three phase inputs have a phase difference greater than 90, i.e., A or B or C > 90. This mechanism can detect wrong connection of the meter or generation of active energy. The NEGP pin output will go active high when negative power is detected on any of the three phase inputs. If positive active energy is detected on all the three phases, NEGP pin output is low. The NEGP pin output changes state at the same time as a pulse is issued on CF. If several phases measure negative power, the NEGP pin output will stay high until all the phases measure positive power. If a phase has gone below the "NO LOAD" threshold, NEGP detection on this phase is disabled. NEGP detection on this phase resumes when the power returns out of "NO LOAD" condition. See No Load Threshold section.
SCF 1 0 1 0 1 0 1 0
S1 1 1 1 1 0 0 0 0
S0 1 1 0 0 1 1 0 0
F1, F2 Min (MHz) CF Min (MHz) 0.013 1.64 0.41 0.41 0.103 0.103 0.026 0.026 0.208 13.1 3.28 6.56 1.65 16.48 0.208 4.16
OUTLINE DIMENSIONS 24-Lead Standard Small Outline Package [SOIC] Wide Body (RW-24)
Dimensions shown in millimeters and (inches)
15.60 (0.6142) 15.20 (0.5984)
24
13
7.60 (0.2992) 7.40 (0.2913)
1 12
2.65 (0.1043) 2.35 (0.0925) 0.30 (0.0118) 0.10 (0.0039) 1.27 (0.0500) BSC 0.51 (0.020) 0.33 (0.013) 8 0 SEATING 0.32 (0.0126) PLANE 0.23 (0.0091)
0.75 (0.0295) 0.25 (0.0098)
45
COPLANARITY 0.10
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AD CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
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PRINTED IN U.S.A.
10.65 (0.4193) 10.00 (0.3937)
C02676-0-1/03(0)

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